1. Field of the Invention
The present invention generally relates to semiconductor memory devices storing information, and more particularly, to a semiconductor memory device suitable for high integration.
2. Description of the Background Art
A semiconductor memory device is used in every device. The storage capacity tends to increase year by year. Increase in the storage capacity leads to increase in the number of elements arranged in a semiconductor device. Therefore, high integration is an important technique in order to dispose a number of elements in a shape similar to a conventional one.
Description will be given hereinafter of a conventional semiconductor memory device with reference to the drawings. FIG. 23 is a diagram showing a configuration of a conventional semiconductor memory device.
Referring to FIG. 23, the semiconductor memory device includes memory array blocks 101, first control circuits 102a to 102c, second control circuits 103a to 103c, column decoders 104, row decoders 105, interconnection portions 106, and a chip 107. Chip 107 is divided into four regions of two rows and two columns. Each region includes memory array blocks 101, first control circuits 102a to 102c, second control circuit 103a to 103c, column decoder 104, row decoders 105 and interconnection portions 106. The regions are symmetrically arranged with respect to the center of chip 107.
Memory array block 101 includes a plurality of memory cells arranged in a matrix, a plurality of bit lines extending in the column direction, and a plurality of word lines extending in the row direction.
First control circuits 102a to 102c each amplify an information signal provided from a bit line of memory array block 101 by a sense amplifier for output of the amplified information signal to an I/O line. First control circuit 102 has a shared sense amplifier configuration, in which one of bit lines of memory array blocks 1 disposed on both sides is selected.
Second control circuits 103a to 103c are connected to first control circuits 102a to 102c through interconnection portions 106 to control operation of first control circuits 102a to 102c.
Column decoder 104 selects a predetermined sense amplifier included in first control circuits 102a to 102c in response to an externally applied address signal.
Row decoder 105 activates a predetermined word line corresponding to the externally applied address signal.
Arrangement of each block will now be described. First control circuits 102a to 102c are regularly disposed at a pitch L, with corresponding memory array blocks 101 interposed therebetween. Therefore, the number of first control circuits 102 is larger than that of memory array blocks 1 by one. Column decoder 104 is disposed in contact with the innermost first control circuit 102c. Row decoder 105 is disposed in contact with corresponding memory array block 1. Therefore, row decoder 105 and memory array block 1 are equal in number. Second control circuits 103a to 103c are disposed in the row direction of first control circuits 102a to 102c with corresponding interconnection portions 106 interposed therebetween. The length of second control circuits 103a to 103c in the column direction is L'. The outer side in the column direction of second control circuit 103a is aligned with the outer side in the column direction of first control circuit 102a. The inner side in the column direction of second control circuit 103c is aligned with the inner side in the column direction of first control circuit 102c. The center line of second control circuit 103b is aligned with the center line of first control circuit 102b.
The memory array blocks and the first control circuits shown in FIG. 23 will now be described in detail.
Description will first be given of first control circuit 102b having memory array blocks 101 disposed on both sides. FIG. 24 is a first diagram showing a configuration of the first control circuits and the memory array blocks shown in FIG. 23.
In FIG. 24, memory array block 101 includes a word line WL, bit lines BL0, /BL0 (in this specification, drawings and claims, /before BL indicates inversion of BL), BL1, /BL1, and memory cells 125, 126. For the sake of simplification, only two memory cells 125, 126 of a plurality of memory cells, only four bit lines BL0, /BL0, BL1, /BL1 of a plurality of bit lines, and only one word line WL of a plurality of word lines are shown in FIG. 24.
Memory cell 125 includes a transistor Q129 and a capacitor C100. As shown in FIG. 24, the memory cell has a structure of one transistor and one capacitor. Bit lines BL0, /BL0 are connected to first control circuit 102b on the left, and bit lines BL1, /BL1 are connected to second control circuit 102b on the right. As to reading or writing of data from or to the memory cell, a predetermined word line, for example, word line WL is activated by row decoder 105, and data of a selected predetermined memory cell is provided to second control circuit 102b through bit lines, for example, bit lines BL0, /BL0.
Second control circuit 102b includes a sense amplifier 120 and transistors Q121 to Q129.
Transistors Q121, Q122, configuring a first switch, controls connection between first control circuit 102b and bit lines of the leftmost memory cell array 101 in the case of first control circuit 102b on the left.
Sense amplifier 120 differentially amplifies data transmitted to one bit line from a memory cell between the one bit line and the other bit line configuring a bit line pair.
Transistor Q123, configuring a second switch, equalizes potentials of the bit line pair.
Transistors Q124, Q125, configuring a third switch, precharge potentials of the bit line pair to a predetermined potential V.sub.BL.
Transistors Q126, Q127, configuring a fourth switch, transmit data amplified by sense amplifier 120 to the outside world.
Transistors Q128, Q129, configuring a fifth switch, control connection between first control circuit 102b and bit line pair BL0, /BL0 of memory array block 101 on the right in the case of first control circuit 102b on the left.
Second control circuit 102b is configured as described above. Second control circuit 102b selects a predetermined bit line pair out of bit line pairs of memory array blocks 101 provided on both sides by first and fifth switches Q121, Q122, Q128, Q129. After amplifying an information signal of the selected bit line pair by sense amplifier 120, second control circuit 102b transmits the amplified information signal to the outside world through fourth switch Q126, Q127.
Description will now be given of first control circuits 102a, 102c disposed on both ends. FIGS. 25 and 26 are second and third diagrams showing configurations of the memory cell array blocks and first control circuits shown in FIG. 23.
First control circuit 102a shown in FIG. 25 is different from first control circuit 102b shown in FIG. 24 in that the outer contacts of first switch Q121, Q122 are in an open state because memory array block 101 is not disposed on the left side of first control circuit 102a.
First control circuit 102c shown in FIG. 26 is different from first control circuit 102b shown in FIG. 24 in that the outer contacts of fifth switches Q128, Q129 are in an open state, similar to the above, because memory array block 101 is not disposed on the right side of first control circuit 102c.
Therefore, as compared to first control circuit 102b selecting memory array blocks disposed on both sides and amplifying data of predetermined memory cells for output, first control circuits 102a, 102c amplify only data of a memory cell of memory array block 101 disposed on one side for output.
Description will now be given of memory array block 101 in more detail. As high integration of a semiconductor memory device progresses, physical sizes of a memory cell, a word line and a bit line become smaller. Accordingly, it becomes difficult to process uniformly the entire surface of a memory array. By disposing a dummy word line of substantially the same shape as that of a word line used in normal operation and a dummy bit line of substantially the same shape as that of a bit line used in normal operation on the periphery of a memory cell array, the normal word line and bit line are formed in an uniform shape.
FIG. 27 is a diagram showing the configuration of the memory array block shown in FIG. 23. In FIG. 27, the memory array block includes shunt regions 111 of a word line, and memory arrays 110. Memory array 110 is generally disposed in a region surrounded by shunt regions 111 and first control circuits 102. Memory array 110 includes a plurality of word lines, bit lines and memory cells (not shown) used in normal operation. On the periphery of memory array 110, disposed are a dummy word line DWL of substantially the same shape as that of a normal word line and a dummy bit line DBL of substantially the same shape as that of a normal bit line, in order to improve processing precision of a normal word line, bit line and memory cell as described above. As a result, processing precision in memory array 110 is improved, resulting in reduction of the deficiency rate of a normal bit line, word line and memory cell.
Because of the above configuration, the conventional semiconductor memory device has the following problems.
As shown in FIG. 23, second control circuit 103a is connected to interconnection portion 106 at its right side, second control circuit 103b is connected to interconnection portion 106 at its center and second control circuit 103c is connected to interconnection portion 106 at its left side. Therefore, three patterns are required for connection between interconnection portions 106 and second control circuits 103a to 103c, respectively, thereby lowering design efficiency. Since a width L' of the second control circuit must always be smaller than a pitch L of the first control circuit, there exist unused spaces between corresponding second control circuits 103a and 103c, hampering high integration.
Since contacts of first or fifth switch on the side where memory array block 101 is not provided are in an open state, the contacts are charged abnormally, causing malfunction of the device and deterioration of reliability of the device. This problem becomes more significant as charge capacitance of a memory cell is lowered by high integration, resulting in prevention of high integration of the device.
In order to obtain higher integration, it was not possible to maintain uniformity in shape of a bit line, word line and memory cell used in normal operation only by disposing dummy bit line DBL and dummy word line DWL on the periphery of memory arrays 110a to 110d as shown in FIG. 27. It was difficult to achieve higher integration.